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本帖最后由 duguxiaoya 于 2011-1-14 12:34 编辑
Hardware intern - ASIC Design for Test (DFT)
Openings：2
Deadline：2011-01-31
You may refer to the link for applying:http://www.ciscoapi.com
Job Description
Hardware Engineers who participate in the design of complex, high performance and high integration ASICs used in Cisco storage/data center switch products.
Implement Design for Test strategy into the ASICs and responsible for ASIC DFT sign off. Participate in driving new DFT methodology and solutions to improve quality of the ASIC, reliability and in system test and debug capability.
Daily responsibilities include:
•Generate tests which achieve highest possible ASIC component test coverage with lowest overhead.
•Verify all DFT logics and test patterns with simulation and static timing analysis tool.
•Implement and verify advanced DFT logics like logic BIST, high speed interface test logic etc.
•Participate in new DFT methodology discussion and solution generation.
•Work with ASIC design team in ASIC bring up.
Skills Required
•Understand the concepts of ASIC flow.
•Hands on knowledge of simulation and verification debug tools.
•Good knowledge of using Verilog HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
•Experience in ASIC DFT/timing is a plus |
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发表于 2011-1-14 12:32:16