|
|
AMD （上海）DFX部门现在招2016年毕业的实习生，该职位如果表现好，很有可能会转正！
有兴趣的童鞋请尽快将中英文简历发至：shenyong21@sjtu.edu.cn
邮件标题请注明：姓名-毕业时间-一周实习天数-实习周期
RESPONSIBILITIES:
- Responsible for DFT feature and VerifPlan setup.
- DFT area work including,RTL,SMS，timing,Scan,and DV
- Develop test DFT cases and procedure.
- Responsible to use and maintain dft and verification flow.
- Generate test pattern and post silicon validation.
REQUIREMENTS:
- Master.
- Strong logic design and verification back ground.
- Possess knowledge of DFT (RTL,SMS，timing,Scan,and DV).
- Skilled in Perl/tcl, programming.
- Working knowledge in C/C++, makefile is a plus.
- Prefer to have experience in logic simulators and debug tools (vcs,
verdi and etc.).
- Prefer in verilog HDL.
- Problem solving and analytical skills.
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including RTL,SMS，timing,Scan,and DV.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing cl
osure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics |
|
发表于 2014-11-28 14:45:02