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飞思卡尔2015校园招聘 – IC Design and Verification Engineer in Suzhou

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发表于 2015-1-6 15:48:56 | 显示全部楼层 |阅读模式
飞思卡尔2015校园招聘 – IC Design and Verification Engineer in Suzhou


飞思卡尔:公司总部位于美国德州奥斯汀市,并在全球范围内拥有设计、研发、制造和销售机构。飞思卡尔广泛开发先进的技术以及嵌入式领域的专业知识,并带来诸多创新的系统级解决方案。飞思卡尔矢志创新,在知识产权方面拥有超过6000项专利产品系列;公司2013年在研发方面的投资超过7.5亿美元;在全球的20多个国家拥有超过17000名员工,并促进创新和多元化;公司积极使用和搭建通用平台,支持开放标准,推进真正的融合。飞思卡尔是全球领先的芯片制造商并在很多竞争激烈而又充满活力的市场居于领先地位。2013年飞思卡尔全球收入达到41.9亿美元。
飞思卡尔是全球嵌入式处理解决方案、高级汽车电子、消费电子、工业控制和网络市场的领导者。从微处理器和微控制器到传感器、模拟集成电路(IC)和连接,我们的技术为创新奠定基础,构建更加环保、安全、健康和互连的世界。

飞思卡尔领创智能世界。期待你的加入,与我们一起开创下半个世纪,申请邮箱:campus@freescale.com

IC Design and Verification Engineer  
Location: 苏州
Responsibilities:
• Designs and develops digital circuits for Micro-controller.
• Verification in module level and Chip level; define and execute verification plan with full functional coverage.  
• Involved in the Digital IP design and verification, joins the SoC development for ARM Based MCU.
• Doing RTL coding, integration and verification.
• Doing simulation in Gate Level, transistor Level (full-chip spice).
• Create function test patterns for testing engineering.

Requirements:
• Bachelors or Master Degree or University Degree or equivalent from Electronic, Electrical or Computer Science.
• Good language skill in English, Pass CET-6.
• Have knowledge about EDA simulation and synthesis tool as well as VLSI design flow.
• Good knowledge in Verilog, VHDL, System Verilog, System C or E, and script language.
•Good knowledge in RTL code style, full synchronous design style, and knowledge of Design-for-Test (DFT) is a plus.
• Have used Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor digital and/or analog developing  
• Have knowledge about Computer Architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer is a plus
• Prefer know-how of ARM or AHB bus system.
• Prefer experience of formal verification with property scheme, for example SVA (System Verilog Assertion).
• Basic knowledge of Analog and Mix-signal design and simulation is a plus.
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