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要求有工作经验最少1年以上， 有兴趣的同志们可以把简历直接mail我的邮箱enjoyasic@126.com，或者QQ细聊 : 25863883
Job Description:
Responsibility:
• Integrate GPU blocks as chip based on architectural requirement.
• Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
• Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
Requirement:
• MS degree of EE with 1~ 4 years, or bachelor with 3~7 years working experience in ASIC Company.
• Familiar with Verilog RTL design and has experience of large digital ASIC project.
• Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
• Familiar with unix/linux and scripts (tcl, perl etc.)
• Fluent English on talking, presentation and writing documents.
• Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
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发表于 2011-12-8 23:31:50