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Marvell 诚招QA & PCB Layout

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发表于 2012-7-17 16:02:29 | 显示全部楼层 |阅读模式
If you have any interest in the position, please send your bilingual resume as
attachments to  marvell.recruit@gmail.com
Subject of your email should be “Your Name_University_Applied Position Title”

1/ Embedded System QA Engineer
Department: Central Engineering – System
Location: Shanghai
Responsibility:
- Develop test plans according to given project schedule
- Design test cases according to given product requirements or network standards
- Development and maintain automated test software
- Design and deploy test environment including both hardware and software
- Support development team by providing remote access to test scenario and detailed report on found defects

Requirements:
- Bachelors Degree in Computer Science or equivalent, M.S. preferred
- 3+ years experience in automated testing, been through a full-life cycle of automated test software
- Familiar with test planning and test case design
- Familiar with TCP/IP network stack
- Solid experience on device driver, TCP/UDP socket programming and GUI development (Windows/Linux)
- Solid experience on application development (C++ or Java) and SDKs (Visual studio/GNU)
- Familiar with at least one script language (Perl, Python, Shell)
- Familiar with SCM tools (Subversion/Perforce) and build automation software
- Good communication skills in verbal and written English
- Willing to learn, self-starter

Plus:
- Experience on building and leading a team
- Experience with embedded system, RTOS, and low-power system.
- Experience with wireless network and related protocols/standards
- Experience in logic analyzer, oscilloscope, network protocol analyzer, and packet sniffer
- Familiar with web interface design and deployment such as LAMP

2/ Job title: Hardware Schematic & PCB design Engineer
Department: Embedded System Group - CTO Office, Shanghai
Location: Shanghai

Must :
-Excellent hardware debug skills.
-Ability to write and debug drivers in linux-like system on ARM platform.
-Ability to design Schematic and PCB using Cadence Allegro.
-Experience with instruments such as spectrum analyzer, signal generator and vector network analyzer in RF -circuit measurement and tuning.
Nice To Have:
-Experience with ADS.
-Self-motivated, be able to perform multiple tasks under pressure and tight schedules.
-Good communication skills.
-AGPS background is a plus.
-Familiar  with HFSS is a plus.
-BSEE with 2-3 year hardware related experience or MSEE.
Responsibilities:
-Hardware schematic & PCB design.
-Diagnose hardware related issues on customer's design.
-Provide support to customer in resolving hardware and system level issues.
-Cooperate with software engineers to bring up new hardware design.

3\  Job Title: Physical Design Engineer in Shanghai/Chengdu
Department: COT PD
Location: Shanghai/Chengdu
Requirements:
      -BS/MS in EE/CS required.
-Three or more years of hands-on experience in IC physical design, verification and tapeouts.
-Proven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
-Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
-Knowledge of Mentor's Calibre or Synopsys' Hercules runsets or ruledecks creation and debugging.
-Good programming skill. Capable of writing Tcl or Perl.
-Familiar with synthesis, static timing analysis.
-In-depth understanding of fabrication processing steps used in major fabrication industries.
-Self-motivated team worker, good verbal and written communication skills in English.
-Technical and team leadership proffered. Previous management experience highly desired.
-Experience with synthesis, DFT, and verification is preferred.

Description:
-IC implementation from netlist to gdsii, with floorplanning, place and route, timing closure, and physical verification.
-Crosstalk analysis, power analysis, and static timing analysis.
-Write scripts in Tcl to improve productivity.
-As a key member of central physical design team, your will play a important role in assisting multiple Marvell design groups in physical design, verification (DRC/LVS/ERC/Antenna) and tapeout.
-You will have the opportunity to help develop next generation physical implementation flow for
cutting-edge technology.
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