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Job Title: ASIC DFT design Engineer
Location: Shanghai
Job Description:
-Block, IP and SoC level DFT implementation (JTAG, Scan, Mbist and analog/IP test etc.) and RTL integration;
-Participate in test spec/plan definition; create the DFT design document and signoff DFT review checklists;
-Test patterns/vectors generation and verification;
-Interface to backend team on physical design and timing closure;
-Interface to test engineers on ATE and vectors bring-up and debugging;
-Chip DFT quality sign-off
-DFT STA, constraint generation, formal and timing closure
Qualifications:
- DFT design and integration experience
- Hands on DFT implementation experience (Bscan, Mbist, DC/AC Scan, analog IP test circuit integration, IDDQ test, ATPG and test pattern verification)
- Expertise with DFT tools from Synopsy, Mentor, Syntest etc.
- Strong logic design and verification background
- Experience in Synthesis and STA will be plus
- Proficient in Perl, tcl and shell programming
- BSEE degree or above
- Good team work spirit
If you are interested in the position, please send your resume to the following email address: jiangrr@marvell.com
Subject of your email should be: School_Name_Applied position_Information source
Eg.SJTU_Zhang Peng _Data Analyst_BBS
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发表于 2014-12-11 13:37:03