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1、Job Title: ASIC Implementation Engineer
Location: Shanghai/Beijing
Job Description:
- Block, IP macro or SoC level implementation in 28nm or 20nm TSMC/UMC process
- UPF Synthesis with Synopsys DC or DCT/G flows
- RTL2Gate and Gate2Gate formal check with LEC and/or formality tools.
- Working with BE team to timing closure in Primetime-SI on multi-corners and multi-modes
- Ability to build or perfect the EDA-methodology-flow with perl, tcl or shell
- Knowledge on DFT (mbist/scan) will be an added advantage
Qualifications:
- BSEE degree or above
- Strong understanding of synthesis flow using DC/DCT/DCG - for a low power (UPF) and high speed- complex SoC
- Hands on experience with formal verification tools such as LEC and/or formality
- Must have the CTS conceptions in ICC at P&R stage
- Strong STA skills. Must have thorough knowledge on closing timing at unit and top level
- Experience in mbist and scan will be plus
- Proficient in Perl, Tcl and Shell programming
-Good team work spirit
2、Job Title: ASIC DFT design Engineer
Location: Shanghai/Beijing
Job Description:
-Block, IP and SoC level DFT implementation (JTAG, Scan, Mbist and analog/IP test etc.) and RTL integration;
-Participate in test spec/plan definition; create the DFT design document and signoff DFT review checklists;
-Test patterns/vectors generation and verification;
-Interface to backend team on physical design and timing closure;
-Interface to test engineers on ATE and vectors bring-up and debugging;
-Chip DFT quality sign-off
-DFT STA, constraint generation, formal and timing closure
Qualifications:
- DFT design and integration experience
- Hands on DFT implementation experience (Bscan, Mbist, DC/AC Scan, analog IP test circuit integration, IDDQ test, ATPG and test pattern verification)
- Expertise with DFT tools from Synopsy, Mentor, Syntest etc.
- Strong logic design and verification background
- Experience in Synthesis and STA will be plus
- Proficient in Perl, tcl and shell programming
- BSEE degree or above
- Good team work spirit
3、Job Title: Cellphone Modem & SOC ASIC Engineer
Location: Shanghai/Beijing
Job Description: modem:
3G: TD-SCDMA and WCDMA modem development
4G: TD-LTE modem development
SoC: next generation cellphone SoC full design cycle from spec.to mass production. Largest chip inside Marvell.
1) R&D L2/L3 of the above protocol stacks.
2) Integration and Testing with the UE system.
Qualification:
MS degree in microelectronics, or electrical engineering.
At least three years working experience.
Experience in real design projects (front-end or backend) is a strong plus.
Good team work spirit and communication skill. Eager to learn, work and grow in a challenging project.
If you are interested in the position, please send your resume to the following email address: jiangrr@marvell.com
Subject of your email should be: School_Name_Applied position_Information source
Eg.SJTU_Zhang Peng _Data Analyst_BBS
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发表于 2014-12-12 17:06:20