|
|
FW:2009 NVIDIA上海IC layout招募(内部推荐), 有效期15天。
所有简历将仅用于本次IC layout招募，并且您的任何资料将仅被参与本次招募的人员看到。发送简历请至fchang@nvidia.com 工作地点在上海张江，距离地铁站步行大约10分钟。
JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus. |
|
发表于 2009-7-10 15:23:47