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Physical Design Engineer
Education:Masters
Department: Switching R&D – MTSL
Experience: new graduate
Some experience in physical design engineering coupled with a good degree
Skills:
The successful applicants will have exposure to at least some of the following areas:
Digital Soc chip design and implementation
Design automation and analysis using scripting languages, particular Tcl and Perl
Design Flows and the EDA tools, in particular tools from Magma, Mentor and Synopsys.
Sign-off methodology and EDA tools for STA, Noise, Power, etc.
Structured design styles involving placed gates
ATPG tools and methodologies.
Key Responsibilities:
Depending on experience, key responsibilities will involve some of the following:
Development and optimisation of high performance and low power Soc physical implementation methodology
Working with European engineers to do block level and full chip floor planning, timing and power analysis, and P&R
Design consulting in customer's offices on physical implementation tasks
Interfacing with foundry and IP providers on IP imports and test definition.
Would you like to be involved in some of the most complex chips in China? Would you like to work with the most advanced 40nm and 28nm processes? If so, then this job could be for you. We are only looking for the best engineers; those who are willing to put in the extra effort required to stay ahead of the rest; and those who want to be part of the best physical design team in China. If your ambition is to lead the world in technical excellence, then this could be for you.
Please send your resumes to yanghong@marvell.com
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