飞思卡尔半导体招聘IC研发实习生

飞思卡尔

飞思卡尔半导体招聘IC研发实习生
飞思卡尔半导体总部位于美国德克萨斯州奥斯汀市，其设计、研发、生产及销售机构遍布 20 多个国家和地区。在创新、质量和注重实效的企业文化引领下，全球 18,000 名员工齐心协作、锐意进取。秉承让世界更智能的理念，我们始终是嵌入式处理解决方案的领导者。

飞思卡尔在嵌入式处理解决方案领域处于全球领先地位，推动汽车电子、消费类电子、工业电子以及网络设备市场向前发展。从微处理器和微控制器，到传感器、模拟 IC 以及连接器件 ——我们的技术和产品始终为创新奠定基础，让世界变得更环保、更安全、更健康，让人们的联系更加紧密。

本次实习期为6-12个月，针对2016年及以后毕业的硕士研究生，实习生毕业后很有可能成为飞思卡尔的正式成员，还等什么？赶紧报名！

报名方式：大家可以将自己的简历以“工作地点-职位名称-就读学校-毕业年份”为标题将简历发送至：campus@freescale.com ~

具体职位信息如下：
1. Silicon Validation Intern
Location: Suzhou
Responsibilities:
-        Apply skills and knowledge in both hardware and software to perform Pre or Post Silicon validation tasks for Freescale microcontroller products
-        To define the validation plan, and create or execute validation test
-        Design and layout the validation board to bring up new system for fresh IC
-        Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production

Requirements:
-        Master or Bachelor Degree, electronic or microelectronic
-        Working knowledge in C/C++, Makefile
-        Big plus with experience in ARM M0, M0+ and M4 based MCU
-        Big plus with experience in IAR and CodeWarrior debugger Tool
-        With the FPGA development experience is plus
-        Fluent in writing and speaking English
-        Can work efficiently either in a team or an independent environment

2. IC Design and Verification Intern  
Location: Suzhou
Responsibilities:
-        Designs and develops digital circuits for Micro-controller (MCU).
-        Verification in module level and Chip level; define and execute verification plan with full functional coverage.  
-        Involved in the Digital IP design and verification, joins the SoC development for 8 bits, 32 bits MCU.
-        Doing RTL coding, integration and verification.
-        Doing simulation in Gate Level, transistor Level (full-chip spice).
-        Create function test patterns for testing engineering.

Requirements:
-        Bachelors or Master Degree or University Degree or equivalent from Electronic, Electrical or Computer Science.
-        Well communication and Inter-person skill.
-        Good language skill in English, Pass CET-6.
-        Have knowledge about EDA simulation and synthesis tool as well as VLSI design flow.
-        Good knowledge in Verilog, VHDL, System C or E language.
-        Have used EDA tool from Cadence, Synopsis, Mentor digital and/or analog developing  
-        Have knowledge about Computer Architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer.
-        Prefer know-how of ARM or AHB bus system.
-        Prefer experience of formal verification with property scheme.
-        Basic knowledge of Analog and Mix-signal design and simulation.

3. Analog/Mixed Signal Design Engineer Intern
Location: Suzhou
Responsibilities:

-        Responsible for analog / mixed-signal IP  design for MCU product development
-        Independent IP schematic design / analog & mix-signal simulation/ layout design / IP view generation / technical documentation
-        Work with SoC / Backend team on IP integration.
-        Work with test/validation/qualification team on IP validation, characterizations and failure analysis.

Requirements:
-        Master Degree in Electrical or Computer Engineering.
-        Familiar with analog/mix-signal IC schematic and layout design
-        Familiar with design EDA tool: Hspice/Spectre,  Virtuso,  Calibre, Assura, QRC;
-        Familiar with lab equipments and  silicon validation /debug flow
-        Experience in power management module design ( high accuracy bandgap /LDO/DC-DC/…) is a plus
-        Experience in data conversion module design ( ADC/DAC) is a plus
-        Experience in clock generation module design ( crystal osc/ relaxation osc/ /PLL/FLL/..) is a plus
-        Experience with mix-signal circuit modeling & simulation is a plus
-        Good communication skills and team work
-        Good oral and written English skills

4. Digital IP Design & Verification Intern
Location: Shanghai
Responsibilities:
-        Verilog RTL coding for digital IP;
-        IP and Platform level testbench setup, IP verification with both BFM and C;
-        Regression and random testing on RTL and gates;
-        Asynchronous clock boundary crossing analysis and ECO process.
-        Debugging complex system level simulations.

Requirements:
-        Graduate Student in Electrical or Computer Engineering.
-        Familiar with digital circuit design and analysis.
-        Familiar with Verilog HDL.
-        Background in C program language
-        Familiar with computer architecture and organization is a plus
-        Experience on synthesis, timing analysis and formal verification is a plus
-        Familiar with SystemVerilog is a plus
-        Familiar with UVM is a plus
-        Working knowledge of Perl scripting and Makefiles is a plus
-        Working knowledge of UNIX/Linux operating systems a plus