【Marvell 成都诚招实习生】Internship of Physical Design

hwangbo

简历投递：xpzhang@marvell.com
简历主题：渠道-姓名-学校-专业-意向职位
工作地点: 四川省成都高新区天华二路219号天府软件园C区10号楼25层
Job Description
External Description
•        Logic synthesis: including std. cell mapping, timing, power, and area optimization.
•        Physical implementation: including floorplan, power routing, placement, clock tree synthesis, routing, si fixing, drc fixing, timing closure, dfm, Flip Chip Routing ...etc.
•        Physical verification: including low power check, timing analysis, timing eco, xtalk analysis, power analysis, ESD analysis, EM analysis, DRC check, LVS check, ANT check, ERC check ...etc.
•        Tapeout: timing signoff, power signoff, design tapeout... etc.
Qualifications – External
•        MS in ME/EE/CS, major in VLSI, logic design. Good GPA required.
•        Hands-on experience in coding/circuit design or physical design is preferred.
•        Detail oriented, self-motivated and team player.  Good verbal and written communication skills.
•        At least four days a week work in office.
•        To qualify for the job, you should have some or all of the following technical background:
a.      Working knowledge of Digital Circuit, such as CMOS principle, combinational
And sequential gate circuit, Layout and IC manufacture flow.
b.      Working knowledge of HDL, such as Verilog, VHDL and reading them easily.
c.       IC design methodologies using design automation EDA tools, ASIC design flow, and deep sub-micron technology.
d.      Familiarization with scripting programming (Tcl, Shell or Perl) is preferred.
e.      Known any of the EDA tools listed below:
                                                              i.      Synopsys: DC, ICC, PT, StartRC…
                                                            ii.      Cadence: RC, EDI, INNOVUS, TEMPUS, QRC…
                                                          iii.      Mentor: Calibre…

Internal Description
•        Work with the product design group to provide back-end design service for multiple Marvell SOC design groups.
•        Perform some or all of the IC design and implementation, such as physical layout floor planning, power grid design, automatic standard cell placement and routing (APR), clock tree synthesis (CTS), timing closure, power and signal integrity analysis (IR-Drop and EM analysis), layout physical verification (DRC/LVS/Antenna), Flip Chip Routing.
【关于Marvell】
Marvell(纳斯达克代码：MRVL)是全球领先的完整芯片解决方案，旨在实现 “Smart Life and Smart Lifestyle”。Marvell公司拥有从存储、云基础设施、数字娱乐到家庭内容交付的多元化产品组合，将完整的平台设计与业界领先的性能、安全性、可靠性和效率相结合。作为消费电子、网络和企业系统的强大核心，Marvell公司令合作伙伴及其客户始终站在创新、性能和大众诉求的最前沿。Marvell公司致力于提高大众的生活体验，通过为世界各地的用户提供移动性和易于访问的服务，为社交网络、生活和工作增添价值。更多公司信息，请浏览公司网页 www.marvell.com.cn