【实习】恩智浦 IC Backend Design Intern-Shanghai

NXPtalent

【实习】恩智浦 IC Backend Design Intern-Shanghai

IC Backend Design Engineering Intern-Shanghai
If interested, send your CV to elena.tu@nxp.com, specifying the position you applied.

Responsibilities:
-        Responsible for low power SOC physical design.
-        Responsible for die size estimation, floor-planning, power planning and power analysis.
-        Responsible for block level CPF design, Logic/physical synthesis, Clock tree synthesis, place and routing, STA, SI, timing closure.
-        Responsible for DFM, DRC/LVS physical verification.

Requirements:
-        4th year college student or 2nd year of post graduate student.
-        Major in computer science, electronic engineering or equivalent.
-        Good language skill in English.
-        Basic experience in IC physical implementation is a plus.
-        Experience using backend EDA tools; i.e. Cadence Virtuoso, RC, EDI, ETS, EPS, Mentor Graphics Calibre etc is a plus.
-        Relevant experience in the area of digital circuit design is a plus.
-        Good knowledge of C/C++, Perl/TCL, scripts in Linux/Unix environment is a plus.