Alchip 2012 Campus Recruiting

donid

SOC Design Engineer

Location: Shanghai

Primary Responsibility
1.        Design testing logic circuit, including: Memory BIST, scan insertion, JTAG, macro test etc.
2.        Be responsible for physical design of large, complex CMOS chips. Tasks including floor plan, partition, power routing, place & route, static timing analysis, DRC/LVS and other physical verification.
3.        Work with customer design team early in design phase to define good design strategies.
4.        Provide feedback and work closely with product development teams to improve design flow.
5.        Coordinate and work with world wide design teams to ensure on time delivery of design results

Qualifications
1.        Master degree or above in EE major
2.        Related experience with a solid IC design and EDA tool background
3.        Experience in at least one of the following disciplines (the more the better): Design implementation from Netlist in to GDS, Chip level testing, ASIC coding and simulation, ASIC physical layout, IC fabrication and processing
4.        Solid understanding of deep sub-micron signal integrity issues such a cross-talk, IR drop, etc
5.        Capable of handling multiple tasks at one time
6.        Experienced in dft, place & route, static timing analysis, synthesis
7.        Extensive knowledge and experience with Cadence, Synopsys or Magma tools
8.        Extensive knowledge and experience with Synopsys DC,  PT and PTSI tool
9.        Experience with Perl, tcl scripting
10.      Good customer communication skill is a must
11.      Good command of English
12.      Good command of Unix

Please attach your resume in the email and send the email to "bding_sh@126.com" if you are interested in this job. Thanks.