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NVIDIA（英伟达）上海校园招聘补招职位
你还在为错过NVIDIA的网申笔试懊恼吗？你还在因为申请错了职位而后悔吗？
送福利啦！NVIDIA（英伟达）上海校园招聘现补招职位：ASIC Physical Design Engineer.想加入NVIDIA的你们，赶快来投递简历吧！
请将简历发至：campus@nvidia.com
这次不要再错过了哦。
Position: ASIC Physical Design Engineer
Location: Shanghai, China
Job Description：
As a result of the improvement in chip process, design scale and performance/power ratio expectation, physical design for digital chips have huge challenges on high frequency, low power, multiple application modes etc. Effective and high quality implementation of building chips is the guarantee of the company’s competitiveness.
As an ASIC-PD engineer at NVIDIA, you'll be responsible for all aspects from synthesis to tape out, except for DFT and PR, you will face the biggest challenge based on the most advanced processes on building chips in the world.
RESPONSIBILITIES:
- Chip integration and netlist generation
- Synthesis
- RTL/netlist quality check
- Formal Verification
- Constraints creation and validation, timing budget.
- Work with ASIC team to analyze/resolve special timing issues.
- Co-work with PR engineers to implement chip partition and floorplan
- Work in conjunction with RR engineers to achieve timing closure for both partition and full chip level
- Achieve special timing closure, such as io, test, clock etc.
- Function eco creation
- Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
- Flow automation development for above areas
- Methodology in any of above areas.
MINIMUM REQUIREMENTS:
- BSEE, MSEE is preferred
- Project experience in IC design implementation
- Courses taken in circuit design, digital design
- Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is preferred
- Proficient user of Perl or TCL is preferred
- Excellent English communication skill
随着芯片工艺不断进步,设计规模的增大，对性能/功耗比期望的提高，数字芯片物理设计面临着高时钟，低功耗，多应用模式等巨大挑战。芯片的高效和高质量的物理实现是公司竞争力的保证。
作为NVIDIA的ASIC-PD工程师，你将负责从综合到流片除了可测性设计和布局布线之外的所有工作，在芯片实现方面，你将基于世界上最先进的流程面临最大的挑战。
工作职责:
- 芯片集成，网表生成
- 综合，网表质量分析
- 逻辑等价性验证
- 约束文件的创建和验证, 产生底层模块时序约束
- 与前端工程师一起分析解决时序问题
- 与P&R工程师合作完成芯片物理实现模块划分
- 芯片级和模块级时序分析和时序收敛
- 特殊电路的时序分析和时序收敛， 如IO，TEST， CLOCK等
- 产生功能ECO脚本
- 以上领域流程的开发，维护和增强
- 以上领域方法的研究
职位要求:
-电子工程或相关专业硕士生或本科生
-有芯片设计经验
-有相关课程背景：电路设计，数字电路
-有相关EDA工具使用经验者优先：Synopsys (DC/PT/Formality), Cadence (RC/LEC)
-具有脚本编写能力者优先：Perl, TCL
-良好的英语交流能力
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发表于 2013-11-29 12:15:52
