【校招】AMD上海研发中心招聘ASIC前端设计应届生

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AMD上海研发中心热招ASIC前端设计应届生，请感兴趣的把简历发送至 maggie1.zhang@amd.com, 并注明“所应聘职位_姓名_学历_专业_毕业年份及月份”，谢谢。


DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Responsible for RTL design and synthesis of part of system IP
- Run front-end integration flow (synthesis, LINT, DFT, etc.), deliver netlists with good quality. Work with RTL owner and physical design team on timing closure and report check.
- Take part in the RTL design of some system IP blocks. Learn the spec and implement in RTL. Work with verification engineer on debugging.


PREFERRED EXPERIENCE:
- Master in electronics, computer, communication or relative majors.
- Skilled in Verilog RTL design.
- Experience in synthesis, timing analysis and formal verification.
- Experience in ASIC or FPGA projects.
- Familiar with front-end EDA tools and flows.
- Fluent written and verbal English.