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Job Title: Design Engineer
Department: SOC Platform
BU: SOC
Location: Shanghai
Responsibilities:
Understanding architecture, micro-architecture, protocols, and execution of the projects;
RTL coding, Verification, synthesis, timing etc;
Documentation;
Work closely with FPGA team for pre-silicon prototyping;
Work closely with software team for driver developments;
Traveling to US is not mandatory, but sometimes required.
Qualifications:
MS, PHD in EE;
Good understanding of digital IC design;
Knowledge of Verilog design;
Good team work spirit and problem solving skills;
Knowledge of System Verilog and VMM is a plus. |
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