7.2 Digital circuit design engineer(数字电路设计工程师)(上海/南京)
岗位职责:
1)Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2)Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
任职资格:
1)Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2)Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred.
3)CAD and script capability such as Python/Perl/Shell is preferred.
4)Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5)Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6)Self-motivated and hard work.
7.3 IC Frontend design engineer(芯片前端设计工程师)(南京)
岗位职责:
1)RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2)Design flow/methodology development and innovation for front-end design challenges.
3)Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任职资格:
1)MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2)New graduate or 3+ years working experience.
3)Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4)Familiar with tcl/Perl/Python program.
7.4 IC Physical design engineer(芯片物理设计工程师)(南京)
岗位职责:
1)Physical implementation of advanced technology chips.
2)Design methodology development and innovation for advanced technology challenges.
3)Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.
4)Be responsible for advanced node PPA benchmark, and solution development.
5)EDA tool new features enablement.
6)Customer onsite/offsite supports will be required on demand.
任职资格:
1)MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.
2)New graduate or 3+ years working experience in chip physical implementation.
3)Familiar with Synopsys/Cadence APR tools/flows.
4)Familiar with TCL/Perl/Python programming.
5)Experience with TSMC advanced technology is plus.
6)Proven record in production tape-outs is plus.
6)Paper publication records
7.5 Layout Engineer(IP版图设计工程师)(上海)
岗位职责:
1)Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
2)Work on the physical verification (DRC/LVS/Antenna ...)
3)Work on test chip layout design and verification
4)Close cooperation with designers on PPA optimization
任职资格:
1)At least BS Degree of Microelectronics or Physics.
2)Excellent graduate or at least 1 years' related working experience
3)Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
4)Familiar with design rule and layout effect in advanced process.
5)Excellent skills of communication and teamwork are also expected.
6)Programming experience (Perl/tcl skill) will be a plus.
7)Experience in advanced process (n16 and beyond) will be a plus.
7.6 DRC/LVS Development Engineer(DRC/LVS开发工程师)(上海/南京)
岗位职责:
1)Work closely with process RD team to develop DRC/LVS for design readiness.
2)Provide customer support to world-wide leading design house.
3)Initial more innovation to continue optimize development efficiency.
4)Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.
5)Work closely with EDA partner for tool qualification and methodology enhance.
任职资格:
1)Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.
2)Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.
3)Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.
4)Ability to work across teams to drive a solution, problem solver and self-motivated.
5)The ideal candidate will have experience in DRC/LVS development.
6)MS or above in EE, CS related fields.
7.7 SPICE Modeling Engineer(上海)
岗位职责:
1)Test key design for SPICE modeling
2)SPICE model release for advanced and mainstream process
3)Device characterization
4)Customer support
5)Automation development on all SPICE modeling flow
任职资格:
1)Minimum MS degree majoring in EE, Physics or Engineering related fields.
2)Related experience in semiconductor device, measurement, extraction and SPICE simulation.
3)Proficiency in programming language, such as Perl or Python or C++ or VB.Net.
4)Must be effectively bilingual in Mandarin and English.
8.品质暨可靠性工程师(上海)
岗位职责:
1)负责产品质量和可靠性。
2)失效分析、可靠性数据分析、生产质量管理和可靠性评估,研究和开发新的分析方案。
3)与客户沟通,解决产品质量和可靠性问题。
任职资格:
1)化学、材料科学、物理、电气工程或相关科学与工程专业硕士或以上学历。
2)在数据分析和统计开发应用方面有相关学习背景。
9.自动化整合工程师(上海)
岗位职责:
1)支持Fab对智能制造技术和自动化系统的维护和部署。
2)与用户沟通以定义需求、设计、实施和部署系统,并使用软件工程方法对其进行持续改进。
3)质量防御体系管理,KPI跟踪分析,支持用户提高制造质量和效率。
任职资格:
1)硕士学历,工业工程、机械及自动化(嵌入式方向)、计算机科学与工程相关专业。
2)至少在以下领域之一具有较强的技术能力:数据库、JAVA、.NET.、C#、Python、优化算法应用、统计和数学工具(MATLAB、R)和编码。
3)熟悉晶圆厂制造操作者优先。
4)良好的沟通能力,抗压能力强。
5)乐于接受挑战,与他人合作。 |